CARES senior project · status on 2026-11-06

ReXNet-150 Datapath Map

Data flows through ReXNet-150 from the input image to the 2-class answer. The chip runs this as 161 separate operations, one after another. This page shows where those operations sit in the network and which ones we have tested.

Passes now Passes with a chip-design fix Not solved Not tested yet

The whole network

Each box is one part of the network; each small square inside is one chip operation, colored by test status. The image gets smaller (224×224 down to 7×7) while the number of channels grows (48 up to 1,920). Stage 1, the tested part, is the stem and the first 4 of the 16 main blocks. Operation counts come from our full-network firmware. On a narrow screen, scroll the figure sideways.

Inside stage 1: the 26 tested operations in order

Read from top to bottom. Grey arrows are the main data path. Purple arrows are side paths that carry a copy of the data around some operations and join again later.

Side path: a copy of the data taken at the dot and used later

SiLU (the activation after each expand conv and in the stem) is x · σ(x). The chip computes it in two operations: a sigmoid, then a multiply of the result with the original x, which comes in on the left purple path.
Shortcut (block f2): the output of block f1 skips block f2 and is added to f2's result at operation 15. Blocks that shrink the image (f1, f3, f5, f11) cannot do this, because the sizes no longer match.
Squeeze-excite (block f3): a side path computes one weight per channel (operations 20–23). Operation 24 multiplies every value of each channel by that channel's weight.

What each operation does

3×3 conv: Each output value combines a 3×3 patch of every input channel. Stride 2 skips every other position, so the image halves in width and height.
1×1 conv: Mixes channels at each pixel, with no neighbors. "Expand" makes many more channels; "project" brings the count back down.
Depthwise 3×3 conv: Filters each channel on its own with a 3×3 patch. Cheap, and the only operation that looks at neighboring pixels inside a block.
Sigmoid: σ(x) = 1 / (1 + e^−x), squashing any value into 0 to 1. The chip reads it from a table.
Multiply: Multiplies two tensors value by value (SiLU), or every value of a channel by one weight (squeeze-excite).
Average: Turns each channel's whole image into one number, its mean.
Add: Adds two tensors value by value (the shortcut).
Pool, classifier: At the end, the average of each of the 1,920 channels feeds one fully connected layer that outputs the 2 class scores.

The untested blocks f4 to f15

Each one repeats the f3 pattern: expand, SiLU, depthwise, squeeze-excite, project. That is 10 operations.
10 of the 12 blocks also add the shortcut, as f2 does (11 operations). f5 and f11 shrink the image instead and have no shortcut.
They use the same circuits as stage 1, so the fixes found so far apply to them. Their sizes differ: smaller images, more channels.
Block f16 is one 1×1 conv to 1,920 channels plus SiLU. Then pool and classifier.

Each tested operation was run alone, starting from the correct input taken from the model on a PC. Running several operations in a chain, where small errors can add up, is not tested yet.